VPN=(VirtualAddress&VPN_MASK)>>SHIFT(Success,TlbEntry)=TLB_Lookup(VPN)if(Success==True)// TLB Hit
if(CanAccess(TlbEntry.ProtectBits)==True)Offset=VirtualAddress&OFFSET_MASKPhysAddr=(TlbEntry.PFN<<SHIFT)|OffsetRegister=AccessMemory(PhysAddr)elseRaiseException(PROTECTION_FAULT)else// TLB Miss
// first, get page directory entry
PDIndex=(VPN&PD_MASK)>>PD_SHIFTPDEAddr=PDBR+(PDIndex*sizeof(PDE))PDE=AccessMemory(PDEAddr)if(PDE.Valid==False)RaiseException(SEGMENTATION_FAULT)else// PDE is valid: now fetch PTE from page table
PTIndex=(VPN&PT_MASK)>>PT_SHIFTPTEAddr=(PDE.PFN<<SHIFT)+(PTIndex*sizeof(PTE))PTE=AccessMemory(PTEAddr)if(PTE.Valid==False)RaiseException(SEGMENTATION_FAULT)elseif(CanAccess(PTE.ProtectBits)==False)RaiseException(PROTECTION_FAULT)elseif(PTE.Present==True)// assuming hardware-managed TLB
TLB_Insert(VPN,PTE.PFN,PTE.ProtectBits)RetryInstruction()elseif(PTE.Present==False)RaiseException(PAGE_FAULT)
TLB项
上下文切换改变页表基址寄存器(PTBR),设置(Address Space Identifier,ASID)
Since collisions may occur, the hashed inverted page table must do chaining
Assuming a good hash function, the average chain length should be about 1.5, so only 2.5 memory accesses are required on average to translate an address . This is pretty good, considering a two-level page table requires 2 accesses